1. Field
The present disclosure generally relates to integrated circuit design. More specifically, the present disclosure relates to designing integrated circuits having a static low power retention state.
2. Background
Integrated circuits (ICs) are commonly designed using design-for-test techniques such as scan based designs in which scan flip flops are included in the IC designs to facilitate test mode operations of the IC. Scan flip flops are similar to standard flip flops but include a scan input, a scan output and an enable input. The enable input toggles the scan flip flop between an operating mode and a testing mode. When the enable input is asserted, the scan flip flops function in a scan mode in which test inputs and test outputs are transmitted via the scan input and the scan output. When the enable input is de-asserted, the scan flip flop operates as a standard flip flop in which input is received via the data input.
In scan based designs, registers in the design are converted to scan flip flops 102. The scan flip flops 102 may be stitched together, as shown in FIG. 1, to operate as an oversized shift register during a test mode of operation. During the test mode, a shift operation is first performed in which a test vector is shifted into the internal circuitry of an IC design via the scan flip flops 102. The test vector propagates through the combinational logic of the IC's internal circuitry, which is also referred to herein as the “cone of logic” 104. A capture operation can then be performed in which a test response is captured by the scan flip flop 102. The response data from the cone of logic 104 is shifted out while shifting in a next test vector.
During each shift, a large number of scan flip flops toggle simultaneously in response to the test vector input. These toggles cause additional toggle activity throughout the entire cone of logic 104. Toggle activity during a shift can greatly exceed the toggle activity that occurs during the normal operating mode of the circuitry. The toggle activity consumes enormous amounts of power, which can detrimentally affect the correct operation of the circuit during testing, as well as decreasing circuit reliability.
One design-for-test technique for reducing power consumption during shift operations is referred to as “gated-q” design. According to gated-q design, logic gates are added to the circuit design between the q-output of each scan flip flop and the cone of logic 104. A shift line to the logic gates is asserted during shift operations. Assertion of the shift line holds the output from the logic gates to the cone of logic 104 in a single state during shift operations. In this way, the q-output of each scan flip flop is “gated” during shift mode.
An example of q-gating is shown in FIG. 2 in which OR gates 202 gate the scan flop output. The OR gates 202 drive a logic ‘1’ at each input to the cone of logic 204 when the shift line 206 is asserted (e.g., during a shift operation). Because the inputs to the cone of logic 204 are held at a logic ‘1’, the combinational logic circuitry in the cone of logic 204 does not toggle during the shift operation so dynamic power consumption is substantially reduced.
Another example of q-gating is shown in FIG. 3 in which NOR gates 302 hold inputs to the cone of logic 304 in a single state. The NOR gates 302 hold logic ‘0’ at each input to the cone of logic 304 during a shift operation in response to assertion of a shift line 306. An input to each of the NOR gates 302 from the corresponding scan flip flop 308 is inverted so that the NOR gates 302 transmit the same value received from the scan flip flop 308 when the shift line 306 is not asserted. Holding the inputs to the cone of logic 304 in a single state prevents propagation of toggle activity throughout the cone of logic 304 and thereby prevents substantial dynamic power losses.
While the q-gating examples described with respect to FIGS. 2 and 3 substantially reduce power that would otherwise be consumed due to propagated toggling of the combinational logic (e.g., dynamic power losses), IC designs are also subject to static power losses. Static power losses due to current leakage in the combinational logic may be even greater than dynamic power in present IC designs. The term “leakage power” refers to the power consumed by a circuit design due to leakage currents when the transistors of the circuit are in their OFF state.
Leakage power consumed by a logic gate depends on the applied input pattern. For example, FIG. 4 shows a 2-input NAND gate 402 and a schematic diagram 404 of the transistors within the 2-input NAND gate. When a ‘00’ input is applied, less leakage power is consumed, as compared to all other input combinations. This is because both transistors T1 and T2 are OFF. This creates a higher drain to source resistance that results in reduced leakage current and reduced leakage power.
The minimum leakage state of a circuit design is the state of the design that consumes the least leakage power. This occurs when as many possible logic gates or other components are parked in their lowest leakage state, such that the overall leakage power of the circuit is at a minimum. The problem of identifying a minimum leakage state for a given design is a complex problem for which various solutions or approximations are postulated. Such solutions, however, are generally unsuitable for practical applications in designing ICs.